Parent Category: 2019 HFE

*By Ivan Boshnakov, Teledyne Defence & Space, Pieter Abrie, Ampsa Inc.; and Malcolm Edwards, AWR Group, NI.*

**Introduction**

This article presents an effective design approach for high-power and high-efficiency RF and microwave power amplifiers (PAs) based on a novel design method using the concept of maximum-efficiency lines, combined with control of the harmonic load impedances.

The concept springs from first examining two previously reported design methods in which compact nonlinear transistor models were used to perform simulated load pull for the fundamental, second, and third harmonics. This evolves into investigating load-pull results when the harmonics impedances at the intrinsic generator of the transistor model are pre-defined and from there to the concept of maximum-efficiency lines and how to define them using nonlinear simulated load pull.

The Cripps method, extended by Abrie’s “power parameters,” which provides the load-pull power contours and the maximum efficiency lines, is also discussed.

**Designing Exclusively From Load-Pull Data**

The initial compact nonlinear model used in [1] did not have the intrinsic channel model exposed. Therefore, the intrinsic voltages and currents could not be observed directly. Without this capability it was impossible to establish the fundamental-frequency and harmonic impedances required for the power and efficiency targeted over the bandwidth of interest in a straightforward manner [3, 4, 5, 6]. Load-pull simulations were therefore required in order to obtain the optimum load impedances (at the available device model’s reference plane) at a number of passband frequencies.

The selected target areas in Figure 1 were used to synthesize the output matching network. The input matching network was designed to match the input impedance of the transistor as calculated by using the S-parameters of the transistor with the load network in place.

Figure 1 • Fundamental-frequency and second- and third-harmonic load-pull contours generated for the transistor at 2.5 GHz (output power and power-added efficiency [PAE]).

The matching circuit synthesis was performed using a real-frequency synthesis technique to synthesize matching networks to solve the fundamental-frequency, second, and third-harmonic problems defined [9].

Figure 2 compares the simulated performance and the measured performance of the designed amplifier. The simulated and measured performances are in good agreement.

Figure 2 •The simulated and measured small-signal gain, return loss, saturated power, and PAE of the amplifier.

**Model With Intrinsic Current Generator**

A different design approach was presented in [2] to design a 1.8 – 2-GHz amplifier stage. The nonlinear transistor model developed by Modelithics for the 30 W T2G6003028-FL Qorvo gallium nitride (GaN) high-electron-mobility transistor (HEMT) was used to demonstrate this new approach. Unlike the model used in the first design approach, this model enables access to the intrinsic device-channel voltage and current, crucial in this second design methodology.

Figure 3 shows the internal schematic of the nonlinear transistor model. The voltages and currents are measured across the intrinsic current generator and the impedance can be calculated and is plotted in the graph on the right. The output tuner of the load-pull setup controls the fundamental-frequency terminations along with the second- and third-harmonic terminations.

Figure 3 • The load-pull setup and the reflection coefficients at the fundamental frequency and the second and third harmonics.

The second- and third-harmonic load reflection coefficients are pre-tuned for the selected class of operation (Class F in this case), before performing the fundamental-frequency load-pull simulations using Microwave Office circuit simulation software. A near short for the second harmonic and near open for the third harmonic are required for Class-F operation.

The fundamental-frequency reflection coefficient at the output was tuned for maximum power, Figure 3. The input tuner is used to achieve maximum gain at the fundamental frequency. The harmonics impedances at the input were set to 50 ohms in this design.

With the second- and third-harmonic load impedances pre-set for Class-F operation, the fundamental-frequency contours for maximum power and maximum efficiency were generated, as shown in Figure 4 (left graph). These contours were used to define a circular target area (green circle) for the fundamental-frequency load terminations.

Figure 4 • Load-pull contours for maximum power and maximum efficiency for the fundamental frequency (left) and the second harmonic (right).

The fundamental-frequency termination was set at the center of the circle targeted and load-pull contours (constant power and constant efficiency) for the second and third harmonics were then generated. The second-harmonic contours were generated with the third-harmonic impedance fixed to an open circuit, while the second-harmonic impedance was fixed to be a short circuit when the third-harmonic contours were generated. Useful areas of the Smith chart were then selected for the two harmonics. The second-harmonic load-pull contours are shown to the right in Figure 4.

The matching networks were synthesized as before [2]. The manufactured amplifier (1.8 - 2.2 GHz) with measured results is shown in Figure 5, indicating good agreement to simulation. The matching networks were synthesized as before [2]. The manufactured amplifier (1.8 - 2.2 GHz) with measured results is shown in Figure 5, indicating good agreement to simulation.

Figure 5 • The simulated and measured performance using this approach were again in good agreement.

**Load Pull With Pre-Defined Harmonic Impedances**

Based on these results, load-pull analysis with pre-defined harmonic impedances was explored further. The first design method using the Wolfspeed 25-W GaN CGH40025F was used again for this investigation. Figure 6 shows a schematic with a load tuner and a new nonlinear model for the transistor, which provides the ability to measure the voltages and currents across the intrinsic generator. Load-pull simulations were performed with the harmonic impedances (reactances) pre-tuned for Class-B, Class-F, and inverse Class-F operation.

Figure 6 • A new model for the 25 W GaN transistor with access to intrinsic generator is embedded in a load-pull simulation setup.

Figure 7 shows the 2.5-GHz power contours obtained at 5-dB gain compression. The maximum output power at the same compression depth are similar for the three classes of operation (44.7 dBm, 45 dBm, 45.3 dBm). The differences in the efficiency are significant (57.7%, 67.7%, 75.2%). The efficiency is the lowest for Class-B and the highest for inverse Class-F. The intrinsic fundamental-frequency impedance terminations for maximum power for each class are close to the values predicted by the theoretical expressions for the pre-hard-clipped situation where the RF current and voltage just touch the limiting boundaries of the I/V-curves (knee voltage, maximum current and breakdown voltage) [3, 4, 5].

Figure 7 • The class-B, class-F and inverse class-F peak-power points and constant-power contours (left) with the associated intrinsic fundamental-frequency impedances (right) and their theoretical expressions.

The drain efficiency load-pull contours for the three classes of operation were also generated, Figure 8. The efficiency is again increasing from Class-B to Class-F to inverse Class-F. In the graph on the right, power and efficiency contours are superimposed.

Figure 8 • Drain efficiency contours for class-B, class-F and inverse class-F operation (left) and superimposed output power and drain efficiency contours are shown.

**Impact of Harmonic Terminations**

Figure 8 shows a wide area where acceptable tradeoffs between power and efficiency could be achieved, but the area is strongly dependent on the harmonic impedances.

Two additional power contours are shown in Figure 9. The associated second-harmonic and third-harmonic reflection coefficients were intentionally de-tuned to -90⁰ (green trace) and +90⁰ (pink trace), thereby stretching the useful area further.

Figure 9 • Output power contours for the 25 W GaN HEMT with two additional cases of fixed second- and third-harmonic terminations.

The peak-power point for Class-B is close to one of the contours added. Comparing the performance with the same fundamental-frequency termination, but different harmonic terminations, shows the power and efficiency for Class-B operation is 44.7 dBm and 57.7% and degraded to 44.2 dBm and 49% if the harmonics are de-tuned to 90⁰. This extreme case illustrates that the performance can degrade substantially if the harmonic impedances are off-target.

**3D Load-Pull Simulations**

The importance of the effect of the harmonics terminations is illustrated well in [3] and the graphs in Figure 10. 3D and 2D plots of the output power and drain efficiency as a function of second- and third- harmonic reactance values depicts the design sensitivity to harmonic loads based on how the drain-source capacitance is modelled (linear vs. nonlinear). The fundamental-frequency impedance is pre-defined for maximum power from a 10-W GaN HEMT device operating at 2.45 GHz, while the reactance values at the second- and the third-harmonic frequencies are swept. The graphs on the left and in the center show power and efficiency versus the second- and third-harmonic reflection-coefficient angle, while the graph to the right shows merged two-dimensional cross-sections for a chosen performance target (power higher than 10-W power and efficiency higher than 80%).

Figure 10: 3D and 2D (cross sectional) plots of output power and drain efficiency as a function of the second- and third-harmonic reactance values [3].

These graphs show a very wide area of acceptable reactance values for the harmonic terminations and very deep poor-performance valleys, which should be avoided.

The nonlinear transistor models used in some scientific papers are more advanced than the models provided by many transistor manufacturers. In [3] the output capacitor (*C _{ds}*) of the transistor is modelled as nonlinear and it is shown that this substantially widens the useful impedance area for high-power and high-efficiency performance. The nonlinear models provided by most transistor manufacturers are, however, simplified and the output capacitors have fixed values.

Furthermore, commercial models are sometimes not validated even up to the third harmonic of the upper end of the useful fundamental-frequency range. To emphasize the importance of modelling *C _{ds}* as nonlinear, the two graphs shown in Figure 11 [3] compare the results of load-pull simulations with

*C*constant and

_{ds}*C*nonlinear. Modeling

_{ds}*C*as constant leads to more restrictive requirements for the harmonics impedances.

_{ds}Figure 11: Output power and drain efficiency as a function of the second-harmonic and third-harmonic reactance values for a transistor model with a constant Cds (left) and a nonlinear Cds (right) [3].

**Using Power Parameters, Matching Networks Synthesis, and Maximum-Efficiency Lines**

Steve Cripps published a method of plotting load-pull power contours for a transistor stage operated in Class-A mode [6, 7]. The simple closed-form equations and a cascade LC model for the output of the transistor enabled reasonably accurate plotting of the constant-power contours. Cripps also showed that the elliptical shape of the constant-power contours was caused by the hard clipping of the intrinsic voltage and/or current at the I/V-plane boundaries and that they are derived by intersecting constant resistance and constant admittance circles. The constant resistance circle segment is where the intrinsic current clips, while the voltage clips on the constant admittance circle segment.

Figure 12 • The intrinsic load lines from the I/V plane can be mapped directly into external load lines. The power parameters are used to create constant-power contours for the external load line on the Smith chart.

The Cripps load-line concepts were adopted and extended in the specialized commercially available software tool Amplifier Design Wizard (ADW) [9]. The first extension was to use four arbitrary lines to define the load-line boundaries instead of assuming a rectangular load-line area. The problem of finding the external load line associated with the required intrinsic load line was solved by using the power parameters introduced by Abrie [8]. The intrinsic voltages and the intrinsic output current were mapped to the external voltages for any arbitrary linear network. This network usually consists of the full linear model for the transistor (package included) and any network elements (arbitrary) between the transistor and the matching network. The reverse feedback of the transistor is also accounted for in this approach and external feedback is also permitted. Losses (resistors) are allowed in the transistor model, as well as the external network.

Using the complete linear transistor model and the mapping functions of the power parameters, intrinsic load lines can be mapped directly to external load lines at any frequency of interest, with no restrictions on the transistor configuration, feedback, resistive losses, transmission lines, grounding node position, etc. The power generated by the transistor is determined by the intrinsic load line and the load-line boundaries. Constant-power contours can be generated for Class-A, Class-B, Class-AB, Class-F, and inverse Class-F operation.

Load-pull results from a harmonic-balance simulator and the ADW validate the accuracy of this method. The graph on the left in Figure 13 represents the simulated constant-power contours of an amplifier stage in Class-B operation (5 dB into gain compression). The center graph is the load-pull contours produced in the ADW for Class-B operation with pre-hard-clipped load lines. The graph on the right shows the excellent agreement between measurements.

Figure 13 • Comparison of constant-power contours generated using load-pull analysis of nonlinear model (left) to the output power contours generated using the linear model and power parameters (center).

All the points of maximum power and maximum efficiency of the load-pull contours (Figure 14), starting with the peak-power point for Class-B operation, are lined up on a reasonably smooth curve. This curve will be referred to as the maximum-efficiency line. For a given class of operation, the efficiency will increase initially along the maximum-efficiency line as the power is decreased from its peak value. The class of operation can be changed when the peak-power point for that class is reached, at which point the efficiency will jump to correspond to the new class.

Figure 13 • The graph shows the superimposed constant-power and constant-drain efficiency contours generated in Microwave Office software.

The maximum-efficiency points are positioned on the voltage-clipping side, which at the intrinsic generator is on the constant admittance circle segment and is the side with higher intrinsic load resistance. They are also purely resistive and hence lie on the central horizontal line of the Smith Chart. At the intrinsic reference plane, the power contours are perpendicular (vertical) to the central horizontal line of the Smith chart (contours not rotated).

Figure 14: The ADW-derived constant-power contours at four frequencies across the passband are shown with the maximum-efficiency lines.

When the contours are mapped from the intrinsic generator plane to the output of the transistor using the power parameters, the contours shift and tilt, as shown in Figure 15, and some dispersion is in effect, depending on the complexity of the transistor model. By plotting the maximum-efficiency points on any power contour, the designer is able to set and visualize the desired compromise point for achieving the optimum tradeoff between power and efficiency.

Figure 15 • ADW constant-power contours with the markers placed on the maximum drain efficiency points of the power contours.

If a Class-B, Class-F or inverted Class-F stage is to be designed with harmonic control, the fundamental-frequency load line at each passband frequency can be set to the peak-power termination (or a scaled version of it) or can be chosen to be the optimum point on the power contour targeted, or a circular area around it.

The second- and third-harmonic impedances can be specified to be low or high, relative to the fundamental-frequency impedance (near short or near open), depending on the desired class of operation. Exact shorts, opens or harmonic reflection coefficients (continuous modes) will place very stringent demands on the external harmonic impedances and are not required.

**Design Demonstration and Validation**

After extracting a linear model for the transistor, the fundamental-frequency impedances were selected to be the maximum-efficiency points on the power contours targeted (points on the maximum-efficiency lines) at a number of frequencies across the bandwidth. Power levels below the peak were targeted in seeking the optimum trade-off between power and efficiency (Figure 16).

Figure 16: Artwork view of the synthesized output impedance matching network.

Lumped-component load networks were synthesized for different power levels and different combinations of low and high harmonic impedances. These networks were then imported into the simulator for nonlinear simulation and verification. After a few iterations the desired amplifier response was obtained and a final network of mixed microstrip transmission lines and surface-mount components was synthesized. The parasitic elements and the pads of the lumped components and discontinuities of the microstrip network are accounted for automatically during synthesis.

The final version of the synthesized network, Figure 17, was imported into the general simulator design environment for further layout detailing, along with the nonlinear model and its artwork information. Sections of the design were set up for EM simulation and harmonic-balance was used to verify the design.

Figure 17 • Comparison of amplifier maximum power, power gain, PAE, and input return loss for the initial design method (faded traces) and the new design approach.

The simulation results for the new design method are compared with those of the previous design method (faded traces) in Figure 18.

The new design method provides wider bandwidth (~100 MHz to both the upper and lower edges of the bandwidth) with negligible reduction of output power and efficiency.

**Conclusion**

The design approach in this article is based on selecting the fundamental frequency impedances on the maximum efficiency lines of the load-pull power contours. The desired harmonics impedances are also defined. Combined with the extended Cripps load pull method and real-frequency matching networks synthesis technique the approach provides an efficient (fast) design method that is no less accurate than methods that only use nonlinear transistor models and harmonic-balance simulated load-pull data.

**References**

1. Ivan Boshnakov, *“Practical design approach of RF PA for high efficiency using simulated Load-Pull and real-world network synthesis with control of the harmonics impedances”*, AWR PA Forum at EuMW, October 2014

2. Ivan Boshnakov, Malcolm Edwards, Larry Dunleavy, Isabella Delga “*A Simulation-Based Design Flow for Broadband GaN Power Amplifier Design”,* High Frequency Electronics, Match 2016

3. Neal Tuffy et al., *“A Simplified Broadband Design Methodology for Linearized High-Efficiency Continuous -F Power Amplifiers”,* IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 6, June 2012

4. Kenle Chen, Dimitrios Peroulis, *“Design of Broadband Highly Efficient Harmonic-Tuned Power Amplifier Using In-Band Continuous Class-F-1, Class F Mode Transferring”,* IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 12, December 2012

5. Steve C. Cripps, Paul J. Tasker, Alan L. Clarke, Jonathan Lees, Johannes Benedikt, *“On the continuity of High Efficiency Modes in Linear RF Power Amplifiers”,* IEEE Microwave and Wireless Components Letters, vol. 19, no. 10, October 2009

6. S.C. Cripps, *“A Theory for the Prediction of GaAs Load-Pull Power Contours”, *IEEE MTT-S Int’l. Microwave Symposium Digest, 1983, pp-221-223

7. Steve C. Cripps, *“GaAs FET Power Amplifier Design”,* Matcom, Inc., Technical Note 3.2

8. Abrie, Pieter L.D., *Design of RF and Microwave Amplifiers and Oscillators, Artech House,* 2009, ISBN 978-1-59693-098-8

9. *Amplifier Design Wizard,* Pretoria: Ampsa (Pty) Ltd.; http://www.ampsasoftware.com

10. Canning T., Tasker, P.J., and Cripps S.C., “Continuous Mode Power Amplifier Design Using Harmonic Clipping Contours: Theory and Practice”, IEEE Transactions on Microwave Theory and Techniques, Vol. 62, No. 1, January 2014.Understanding Low Loss Coaxial Cables and Their Applications

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