Monday, March 04, 2024

Using High Accuracy Models to Achieve First Pass Design Success - A Transmitter Case Study: Part 2, Power Amplifier Design

Parent Category: 2017 HFE

By Ted Longshore and Larry Dunleavy


Utilizing non-linear transistor models enables the concurrent optimization of gain, power, efficiency, and modulation linearity over the desired operational bandwidth and temperature in cascaded transistor amplifiers. The expense of the required non-linear models is discussed on the basis of cost savings, shortened development schedule, and improved designer productivity.


This two-part article presents a case study in simulation-based RF/Microwave design, using as an example a transmitter design. Part 1 focused on a harmonic filter design using advanced linear component models1. Part 2 illustrates how the use of accurate, non-linear power transistor models can facilitate successful design flows for transmitter power amplifier designs. A two stage telemetry amplifier was successfully designed in a single pass using NI AWR Design Environment software Microwave Office circuit simulation, Microwave Global Models™ as included in the Modelithics® CLR Library, and a non-linear transistor model, as included in the Modelithics-Qorvo GaN Library2.

Non-linear models, load-pull power device data, and/or X-parameter-based3 models for active devices, are provided by many device manufacturers, but not all devices have suitably accurate models or data available for first pass design success. There is also a cost required to develop accurate models, whether the needed model is provided by the manufacturer, developed in-house by the design group, or developed by a third-party model provider4,5. In addition to the technical aspects of the amplifier design example, this treatment includes a cost/benefit analysis of the required models provided through an example Return on Investment (ROI) calculation6. While the transistor model used in this example is available for free to the designer, our ROI analysis discusses the ROI scenario assuming a custom non-linear model needed to be contracted.

PA Design Approaches

Designing a power amplifier requires trading off gain vs. power, efficiency vs. linearity, and return loss vs. bandwidth7,8. Matching a non-linear amplifier to load-pull derived source (Zs) and load (Zl) target impedances is straightforward for designing a narrow band, single stage amplifier at a single bias point, but significantly more difficult when optimizing a multistage broadband amplifier.

Assuming a non-linear device model is available for the transistor(s) of interest, RF and microwave computer-aided-engineering (CAE) tools such as Keysight’s ADS or NI AWR Design Environment can accurately simulate non-linear circuits, facilitating the design of the input and output matching circuits to optimize gain, output power, efficiency, modulation linearity, and even harmonic levels across the entire frequency band. Unfortunately, few manufacturers supply non-linear models for all of their devices, leaving the engineer to decide whether to develop his own non-linear model, or rely on the Zs and Zl provided in the device datasheet and then build and optimize the prototype on the bench. When using the load-pull Zs/Zl approach, the design and development of a new transmitter typically involves building a prototype and two or more revisions of the complete PCB, with a total development period that may be as long as 12 months. In-house development of a non-linear model requires specialized equipment, expertise and time. Another alternative is to contract a custom non-linear transistor model to be developed by a third party model provider.

Amplifier Example

The requirements for the medium power telemetry transmitter example to be examined here include a frequency range of 2200 to 2400 MHz, minimum output power of 1 W at 85°C, and maximum current draw of 300 mA at 12 V. Adding the insertion loss of the harmonic filter1 and desired design margin, yields a final stage output power design goal of 32 dBm at 25°C. Because the shaped offset QPSK (SOQPSK) modulation for this application is constant amplitude, the amplifier is operated in a compressed mode. The allowable size for the complete transmitter is 2.8 in2, with 0.5 in2 allocated to the driver and final stage RF circuitry.

The Qorvo TGF2965-SM, which is an input matched 32 V GaN transistor rated at 6.0 W was chosen for this application. The small size and integrated input match on this device are important to meeting the stringent size requirements of this transmitter, and the surface mount package facilitates manufacturing. This transistor provides margin if the output power requirements increase in the future. For even higher power future applications, the 10 W TGF3015-SM can be substituted for the TGF2965-SM, thereby leveraging this design effort for additional product offerings. Accurate non-linear models for both of these transistors are included along with about 55 other models in the Modelithics-Qorvo-GaN Library2.

Because of its small size, high gain, and low current consumption, the TGF2965-SM was also chosen for the driver stage on this transmitter. This is overkill for this 1 W application, but works well for it when operated at a lower supply voltage. It is also appropriate for a higher power 6 W version described below when operated at the recommended supply voltage. This design also incorporates a bandpass filter to reduce the transmit noise level at GPS L1 and L2 bands (Figure 1).

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Figure 1 • Transmitter Amplifier Block Diagram.

Zs/Zl Data-Based Final Stage Design Effort

The first effort is to determine the optimal input and output match which produces the desired gain, output power, and efficiency across the operating frequency. Typically, without non-linear models, this is completed using a load-pull setup, or manufacturer published Zs and Zl load impedance. Then a proto board is built to replicate that optimal match, with the component values and the PCB layout tweaked for best performance. This is a time-consuming and iterative effort, and it is difficult to know whether the resulting design is optimal, especially for broadband cascaded amplifier applications. It should be mentioned in the absence of a non-linear model or load-pull data, knowledgeable  designers can for some applications proceed to achieve reasonable starting point designs using load-line  methods combined with small-signal data9.

Model-Enabled Final Stage Design Effort

If an accurate non-linear model exists for the transistor of interest, then it is possible to directly optimize the transistor circuit for optimal performance, rather than re-creating the predetermined source and load impedances. Starting with a non-linear model, provided by Modelithics for the Qorvo TGF2965-SM device, the final stage input and output match was optimized for performance across the 2200 – 2400 MHz operating bandwidth using the AWR DE Harmonic Balance HBTUNER tool (Figure 2). To allow for higher power versions of this transmitter with minimal changes to the circuitry, the output match was optimized to maintain high efficiency at 32 dBm output power at a reduced drain voltage of 12 V. Optimizing gain, output power, and efficiency at this substantially lower Vdd is only possible due to the accurate non-linear transistor models, which ideally would also be validated across the range of intended operating voltage for best confidence. This was not done for the effort described below in which a 32 V optimized model actually worked quite well at 12 V.

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Figure 2 • Final Stage Schematic with HBTUNER in Place of Actual Load Matching Circuit.

This flexibility of model applicability points to a strong advantage of properly developed non-linear models over data-based models or design approaches. While efficient design flows may be possible based on load-pull Zs/Zl data,  data is needed at all of the specific frequencies and bias conditions desired. Whereas a non-linear model, validated at a subset of desired conditions, can often be extrapolated with good accuracy to produce simulations at any desired frequency and bias condition, within the range of validity of the model.

Figure 3 shows nearly +33 dBm output power at 61 % efficiency and compressed gain of 11 dB at an input power of +22 dBm. The plot also shows the decrease in output power and efficiency, and the increase in gain as the input power is reduced in 2 dB steps to 16 dBm. No attempt was made to optimize the matching at the harmonic frequencies for even higher efficiency.

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Figure 3 • Final Stage Gain, Output Power, Efficiency at Vdd = 12 V, Pin +16 to +22 dBm.

Figure 4 shows the optimized load impedance at this output power. This will be used as a design goal when the HBTUNER tool is replaced by actual output circuitry.

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Figure 4 • Optimized TGF2965-SM Output Load Impedance at 2.3 GHz.

Minimizing the overlap between non-zero current and non-zero voltage is the key to optimizing transistor efficiency through “waveform engineering.” The non-linear transistor model utilized in this simulation provides an inspection node that enables visualization of the simulated voltage and currents at the intrinsic ports of the transistor model. This facilitates optimization of efficiency when used in concert with the HB tuner tool. Figure 5 shows that the drain voltage for the final stage design is at a maximum when the drain current is at a minimum, indicating high efficiency.

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Figure 5 • Transistor Die Simulated Drain Voltage and Current at Intrinsic Reference Plane.

The next step is to replace the HB tuner tool with discrete and distributed components to present the same optimal ZL to the transistor drain, and then re-optimize the input and output match for optimal performance across the operating frequency. This is shown in Figure 6. The series inductors are used in the output match instead of a transmission line to reduce the physical layout area, and to facilitate implementation of higher power amplifier versions using the same PCB. The optimization of the best values for the surface mount capacitors, inductors, and resistors included in the matching bias and stabilization networks is facilitated with the part-value scalability of the Microwave Global Models mentioned earlier.

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Figure 6 • Final Stage Amplifier, 1.5 W.

Design of Cascaded Amplifier

After the final stage matching is complete, the driver stage and an interstage surface mount bandpass filter, are introduced. If transistor models are not available, this can be accomplished by matching input and output impedances to 50 ohms at the center frequency, and then cascading them together. However, the impedances of the matched driver and final stage circuits are close to 50 ohms only at that center frequency. Given that most designs operate over a 10 % or larger frequency bandwidth, a significant variation in gain, linearity, efficiency, and output power can be expected after cascading devices together due to the variation in source and load impedances presented by the devices to each another.

Since non-linear transistor models are available for the chosen transistor, it is straightforward to simultaneously optimize the cascaded non-50 ohm driver stage output match, bandpass filter, and final stage input together using the computer simulation (Figure 7), without building and tuning a hardware prototype. Note, the 5 ohm resistors provide placeholders on the PCB for gain adjustment, if necessary.

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Figure 7 • Amplifier Top Level Schematic, Including Bandpass Filter in Interstage Network.

As shown in Figure 8, the simulated gain, output power, and efficiency are flat across the frequency band as the input power is increased in 2 dB steps from 0 to +8 dBm at a drain voltage of +12 V. The levels outside of the passband are reduced by the bandpass filter. At a drive level of +8 dBm, the gain of the cascaded stages is over 3 dB compressed at 24.4 dB, the output power is 32.5 dBm, and the multi-stage efficiency is 47.8 %, thereby meeting the design goals.

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Figure 8 • Amplifier Gain 1.5 W, Output Power, and Efficiency after Optimization for 12V Operation.

Recall that this design has a maximum current requirement of 300 mA at 12 V, at 32 dBm output power. The simulated current draw at +6 dBm input power, which produces 31.9 dBm output power, is 54 mA (driver) + 227 mA (final) = 281 mA, as shown in Figure 9. Knowing the current draw of the non-linear components early in the design process provided assurance that the customer specifications will be met without building a prototype.

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Figure 9 • Driver and Final Stage Non-Linear Current Draw.

The level of the harmonics can be simulated using the non-linear model, as shown in Figure 10. In this case, the final stage output match was adjusted slightly to compensate for the return loss of the harmonic filter and to reduce the level of the fourth harmonic. Given the simulated harmonic levels above, and maximum permissible harmonic level of -25 dBm for the second and third, and -80 dBc for other harmonics, the requirements for the harmonic filter can be determined. Including a 5 dB margin, the design parameters for this filter are +13.5 dBm - (-30 dBm) = 44 dB rejection across 4.4 to 7.2 GHz, +30.5 dBm - 85 dBc - 11.1 dBm = 66 dB rejection 8.8 to 9.6 GHz, and 55 dB rejection for higher frequencies. As described in Part 1 of this article, a combined discrete and distributed harmonic filter was designed to meet the above requirements, and was incorporated into the simulation. Appending the filter designed in part 1 of this article to the output of the PA reduces the simulated level of the harmonics below the required levels, as shown in Figure 11. The ability to determine the requirements of the harmonic filter while still in the “paper” design phase is a key enabler for a successful first-pass transmitter design, since the harmonic filter is an integral part of the transmitter.

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Figure 10 • Simulated Amplifier Harmonics Before Adding Harmonic Rejection Filter.

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Figure 11 • Simulated Amplifier Harmonics After Adding Harmonic Rejection Filter.

High Power Version

In order to provide for possible changes in product requirements, this 1.5 W amplifier was optimized with a drain voltage of +12 V. Thisfacillitates an increase in power capability to 6 W with mimimal matching changes. In this example, the output power on this cascade can be increased to +38 dBm, without changing the PCB, by increasing the drain voltage on the driver and final stages from +12 V to +32 V, and adjusting the values of the discrete components, as shown in Table 1.

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Table 1 • Voltage and Component Value Comparison of 1.5 W and 6 W Amplifier Designs.

Figure 12 shows a compressed output power of +38 dBm at a nominal cascaded amplifier gain of 28 dB, and efficiency of 48 % for the 6W, 32V design version. Note the 2.5 dB increase in gain due to the higher drain voltage, which reduces the need for additional gain stages to support the higher output power level. This is an excellent way to leverage the design effort into two distinct high efficiency amplifier products.

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Figure 12 • Amplifier Gain 6 W, Output Power, and Efficiency after Optimization for 32V Operation.


As shown in Figure 12, the design engineer can optimize the circuit performance for a particular application given simulation capability and component models that accurately predict the operating performance. From this point, it is easy to redesign the amplifier for a different frequency band or power level to meet customer requirements.

Although not required for this application, the degradation of the modulated transmit signal Error Vector Magnitude (EVM), and increase in Adjacent Channel Interference, can be simulated using a tool such as National Instruments’ Visual System Simulator (VSS), or Keysight Technologies’ ADS Envelope Domain Simulation, since the bias points, matching, and drive levels have been determined.

PCB Fabrication and Measurement

The RF amplifier portion described above is only a small section of this single board transmitter, which also includes gate bias circuitry, synthesizer, modulator, attenuator, DC power converters and regulators, FPGA, etc. However, these items are common from one transmitter to another, require minimal design effort, and entail minimal risk. When developing a new transmitter, Quasonix typically builds the entire transmitter, rather than prototypes, relying on the accuracy of the RF simulations, including the component models, to ensure success. Because this project was on a very tight schedule, it was decided to build a prototype of the RF section of this transmitter while waiting on a finalized customer specification. This prototype board, which contains the amplifier and filter circuits described above, as well as the harmonic filter described in part 1 of this article, is shown in Figure 13.

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Figure 13 • Complete Amplifier Layout with Harmonic Filter (left) and Fabricated Board with pigtails (right).

Amplifier Measurement

The large signal (compressed) gain of the cascaded driver, bandpass filter, and final stages were measured using short pigtails connected to the PCB, as shown in Figure 13. The final stage transistors were biased to the manufacturer’s recommended 25 mA drain current at a 12 V drain voltage, while the driver stage was biased to 30 mA for additional gain. The pigtail insertion loss is de-embedded from the measure data discussed next.

S21 at power levels of -10 dBm and +8 dBm is shown in Figure 14, which clearly shows very good agreement between the simulated and measured compressed gain in the 2.2 to 2.4 GHz filter passband. The higher measured gain at -10 dBm input power is a result of the sensitivity of the small signal gain to the transistor bias current while operating in the linear range, and the fact that the simulation model was derived at 32 V operation instead of the 12 V bias in this design. The discrepancy between simulated and measured responses outside of the passband is due to sharper rolloff of the actual filter compared to the S2P data file used in the simulation downloaded from the Mini-Circuits website. (A model for this component has not yet been added to the Modelithics COMPLETE Library and the test board used for the S2P file was different than that on the PA board.)

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Figure 14 • Simulated and Measured Power Gain -10, + 8 dBm Input Power.

The simulated and measured output power at + 8dBm input is shown in Figure 15. There is very close agreement across the filter passband, especially considering that the TGF2965-SM model was created based on the manufacturer’s rated +32 V drain voltage, compared to the +12 V drain voltage used in this application.

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Figure 15 • Simulated vs. Measured Output Power +8 dBm Input Power.

The output power vs. input power, provided in Figure 16, shows excellent agreement between simulated and measured output power, including gain compression at the higher power levels. The +12 V current draw shows excellent agreement at lower power levels and diverges slightly near compression. The measured efficiency is higher than simulated in the low to mid power range due to the higher gain (and thus higher output power) describe above. The data below does not include the harmonic filter losses.

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Figure 16 • Measured Output Power, Current, and Efficiency vs. Input Power.

Example Return on Investment Analysis

An estimate of the design cost and schedule impact with and without adequate models is presented in Table 110. Based on designer experience, it is estimated that it would take two additional iterations to complete the PA design without adequate transistor and passive component models. Table 2 shows a summary of the estimated cost, schedule, and productivity improvement of using accurate models for this design example. As mentioned in this case, the device manufacturer has sponsored free access to the needed non-linear model for this design. However, for the purposes of illustration, we have assumed an investment cost of $25K for the needed models. Actual development cost of a non-linear model depends on many factors, including fixturing requirements, complexity and quantity of measurements needed for extraction and validation, and range of operating conditions and desired simulation requirements of the final model.

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Table 2 • Example Cost and Schedule Estimates for PA Design Completion Without/With Sufficiently Accurate Models.

From Table 3 one can conclude, on the basis of strictly cost, the design cost savings would nearly be justified on the basis of a single design using the models. Certainly the remaining $2.5K cost difference would be justified quite easily on the basis of the schedule improvement from 28 weeks without accurate models, to 11 weeks with models, due to the first pass success that was achieved in the presented design example. Of course, if the same models could be used for even one more such design, the model investment cost would also be fully returned with a significant engineering productivity improvement as well.

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Table 3 • ROI Results Summary Showing Estimated Cost Savings/Schedule Impact of Designing Example PA with Accurate Models.

While not specifically addressed here in quantitative fashion, an analogous ROI analysis could be performed for the case of a manufacturer investing internally or externally in high accuracy models to support their customers. Due to cost, schedule, and other considerations, today’s generation of engineers tend to favor devices that already have accurate models available. From a device manufacturer’s perspective, the model investment cost is, for many markets, becoming a minimum entry fee to ensure consideration of a device for a new design application.


Accurate simulations of microwave circuits can be computed if the component parasitics and non-linearities are included in the simulations. Traditionally provided transistor Zs and Zl source and load impedances generally allow optimized design of a single stage amplifier at specific frequencies. Non-linear transistor models facilitate the simultaneous optimization of gain, output power, efficiency, and linearity across the desired frequency band even for cascaded amplifiers. These models can substantially reduce the development schedule and cost for new amplifier programs. In the presented two stage, 1 watt PA example, a first pass design success was realized with excellent measured to simulated agreement and rapid cycle time. With this approach, an existing design can be easily optimized to meet other customer requirements with minimal development cost and risk.


Quasonix, Inc. ( produces telemetry transmitters ranging in size from the nanoPuckTM described in this article, to higher power multi-band, multi-mode models at power levels up to 25 W, as well as telemetry receivers and precision drive antenna systems.

Information about the Modelithics CLR Library and Modelithics-Qorvo GaN Library models used in this work can be found at or by email at

About the Authors

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Dr. Larry Dunleavy co-founded Modelithics, Inc. in 2001 to provide improved modeling solutions and high quality microwave measurement services for radio and microwave frequency circuit designers.

He is currently serving as President and CEO at Modelithics. He also maintains a position as a Professor within University of South Florida’s Department of Electrical Engineering, where he has been a faculty member since 1990. In this role, he has been teaching in the area of RF & Microwave circuits and measurements for over 26 years. Prior to this he worked as a microwave circuit/MMIC design engineer at Hughes Aircraft and E-Systems companies.

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Ted Longshore graduated with a BSEE from the University of Cincinnati, and an MSEE from Illinois Institute of Technology, and has been working in the field of radio communications for nearly 30 years. He started his career working on cellular base stations and handsets at both Motorola and then Ericsson, and more recently on military electronics at Pole/Zero and NuWaves Engineering. In his current position at Quasonix he develops transmitters for telemetry applications.



1 T. Longshore and L. Dunleavy, Using High Accuracy Models to Achieve First Pass Success- A Transmitter Case Study:  Part 1 Harmonic Filter Design, High Frequency Design, August 2017.

2  L. Dunleavy, H. Morales, C. Suckling and K. Tran, “Device and PA Circuit Level Validation of a High Power GaN Model Library,” Microwave Journal, Aug. 2016. See also .

3 X-parameters is a trademark of Keysight Technologies.

4 Mike Golio and Jim Cozzie, “Who Pays for Characterization?: The Final Dilemma for MESFET Modeling,” 48th ARFTG Conference Digest, Fall 1996.

5  L. Dunleavy, “Modeling-The Hot Potato In the RF & Microwave Industry,” Microwave Product Digest, April 2002.

6  L. Dunleavy, “Everyone wants better models, but where’s the ROI?,” High Frequency Design Magazine, March 2017.

7  S. Cripps, “RF Power Amplifiers for Wireless Communications,” Artech House, 1999.

8  F. Giannini and G. Leuzzi, “Nonlinear Microwave Circuit Design,” John WiIey & Sons, 2004.

9  S. C. Cripps, “A Theory for the Prediction of GaAs Load-pull Power Contours,” IEEE MTT-S Int’l Microwave Symposium Digets, 1983, pp221-223.

10  Analysis completed with ROI calculator that can be accessed on Modelithics website at: .

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