Parent Category: 2016 HFE
By Peter Delos
Introduction
Phase Locked Loops are a fundamental building block in Frequency Synthesizer Design and routinely used in many applications. Much literature exists on design and simulation methods. A critical aspect of phase locked loop design for low noise applications is a clear and intuitive understanding of the noise contributions of components in various parts of the loop. This area seems to be less understood and not explicitly stated in much of the literature. Derivation of noise transfer functions and some key points for phase locked loop noise analysis is provided along with a simulation and measured example.
Phase Locked Loop Control Model
A basic phase locked loop block diagram is shown in Figure 1. The phase detector produces a signal proportional to the phase difference of the two input signals. The integrator adjusts the VCO tuning voltage to minimize the output of the phase detector and thus phase locks the VCO to a reference input signal. References [1-3] provide detailed descriptions of the phase locked loop process.
Figure 1 • Phase Locked Loop Block Diagram.
The phase locked loop circuit of Figure 1 can be constructed in a control system block diagram form as shown in Figure 2. Again, references [1-3] provide thorough derivations of this method. Every component in the loop adds noise to the circuit. Noise sources can be added to the control model as shown in Figure 3. Noise transfer functions will be derived for each contributor to overall output phase noise.
Figure 2. •Phase Locked Loop Control Diagram.
Figure 3 • Phase Locked Loop Noise Sources.
Loop Filter Considerations
Many forms of loop filters exist and have been demonstrated. For this analysis, a loop filter of the form shown in Figure 4 is assumed. This form is typical of many used in low noise phase locked loop design. Filter Gain is set by R1 and RF. CF forms an integrator below the zero set by CF and RF. RLP and CLP form a low pass filter that is typically set above the PLL loop bandwidth.
Figure 4 • Loop Filter Structure.
A typical response of this filter is shown in Figure 5. The Loop Filter response can be considered in three general regions. The 1st region is an integrator. Loop gain in this region provides the mechanism for the VCO to track the reference oscillator. In order to ensure stability, a zero is typically applied in the loop filter forming the middle region of nearly constant gain. An additional pole after loop bandwidth provides additional filtering of the reference noise and forms the third region of additional filtering.
Figure 5 • Loop Filter Response.
These regions have either a constant gain or a constant roll-off. The constant gain region can be written as KF. The constant rolloff regions are integrators and can be written as KF/s . Note that KF is different in each region, but is a constant that can be used in evaluating the PLL transfer function for each region. Considering the loop response based on these regions can provide rapid insight to noise contributions from various parts of the loop.
Noise Transfer Functions Derivation
Each noise source can be considered in terms of a traditional feedback system as shown in Figure 6. In the case of a PLL, the forward path A(s) will be the components between the noise source and the PLL outputs. A(s)B(s) represents the closed loop path. Noise transfer functions will be derived with this method.
Figure 6 •Transfer Function of a Feedback System.
Starting with the Reference noise, we can write the forward gain A(s), and feedback B(s) as;
The reference noise transfer function becomes
In the frequency offset region where the loop filter is a constant gain, KF, the loop filter becomes
This is 1st order low pass function. The bandwidth of this low pass filter is the PLL loop bandwidth and is
In the frequency offset region where the loop filter is an integrator KF/s,the loop filter becomes
Equation 5 is a 2nd order low pass function with no damping. An important observation with this equation is that a loop filter of on ideal integrator will be unstable. In practice a zero is added before the PLL loop bandwidth to bring the transfer function closer to equation 3. To get additional rejection above the loop bandwidth an additional pole can be added to ensure a 2nd order roll-off.
Figure 7 • Reference Noise Transfer Function.
Figure 8 • VCO Noise Transfer Function.
Figure 9 • Loop Filter Noise Transfer Function.
Figure 10 • Phase Detector Noise Transfer Function.
An important phase noise point to note is below the loop BW, the transfer function has a gain of N. This gain is a voltage gain and causes a phase noise increase of the reference phase noise by 20logN below the PLL loop BW.
Noise transfer functions from every source can be derived in a similar approach and are summarized in the following figures. The reference noise transfer function is repeated for completeness. Noise from the divider has the same forward gain as noise from the reference, therefore the same transfer function, and is not explicitly shown.
Key Points and Summary Table
Two key points for design considerations include:
1) Loop Filter response should be in the constant gain region at the loop bandwidth. The gain can be determined by (4) which is rewritten,
Once the gain is determined, R1 and RF of Figure 4 can be determined. Next CF is set so the pole in the feedback is below the loop bandwidth. Finally RLP and CLP are set for a pole above the loop bandwidth. Further stability considerations are provided in [1-3].
2) Noise of all components, except the VCO, have a noise gain proportional to 20logN in the regions with no attenuation.
A final summary is shown in Figure 11.
Figure 11 • Summary Table.
Simulation and Measured Data
A practical example to demonstrate the noise transfer function concepts will be shown for a low noise 100MHZ VCO phase locked to a 10MHz reference. Measured data will be compared to the simulation results.
Many PLL simulators exist. For this example, ADS was chosen for maximum flexibility to demonstrate the concepts, and the PLL model is shown in Figure 12. ADS provides an example project to use as a starting point [6]. Phase Noise is modelled for the Oscillators and the Frequency Divider. Voltage noise is modelled for the loop filter.
Figure 12 • 10MHz to 100MHz PLL Model in ADS.
Noise units are an important parameter to keep straight at various points in the loop. The filter is in the voltage domain with noise units of nV/℘Hz. The oscillators are a frequency and the model tracks frequency noise in units of rad/℘Hz. The detector and oscillator constants (KD and Ko) provide the conversion between noise in the voltage domain to noise in the frequency domain. The desired output is phase noise tracked with units of
dBc/Hz. The conversion to phase noise is calculated directly from the phase noise definition[ 7 ].
For a cosine wave with phase noise
The Spectral Density is the power within a bandwidth divided by the bandwidth and is given by
Phase Noise is defined as
which represents the single sideband phase noise of the carrier
Phase Noise is specified in dBc/Hz from 10log(L(f)).
The first step is determining the optimum loop BW for the application. Typically the loop bandwidth is set near the frequency where the reference noise crosses the VCO noise. This needs to be done at a common frequency to account for the 20logN increase in reference phase noise, see case 1 of Figure 7. For this example, the phase noise of the free running VCO and the reference oscillator multiplied to the output frequency are both shown in Figure 13.
Figure 13 • Phase Noise of Reference Oscillator and VCO.
For this design the loop bandwidth was chosen to be slightly higher than the optimum phase noise BW for vibration considerations and set to about 75Hz. The simulation of the noise transfer functions from both the reference oscillator and the VCO are shown in Figure 14. Two things to note both consistent with the earlier derivations are:
Figure 14 • Noise Transfer Functions of the Reference Oscillator and the VCO.
1) The Reference has a low pass characteristics with a gain of 20*log(N), where N is the division in the feedback.
2) The VCO has a high pass characteristic.
Next noise contributions of all the components in the loop are considered. Figure 15 shows the noise contributions from all the loop components including the reference oscillator, the VCO, the phase detector, the frequency divider, and the components of the loop filter. By tracking noise contributors this way, components can be chosen for lowest noise where necessary and ignored when well below the levels of the dominant contributors.
Figure 15 • Loop Component Contributions to Overall Phase Noise.
These methods were used in a recent synthesizer design. Figure 16 is a comparison of the simulated vs measured results of the phase locked loop output. The results show very good correlation demonstrating that by accurately tracking the noise contributions of all the parts, predicted results can be achieved.
Figure 16. Phase Noise Measured vs Simulated.
About the Author
Peter Delos is a principal RF/RFIC Engineer in the Lockheed Martin Microwave Center at the Moorestown NJ facility. He received his BSEE from Va Tech in 1990 and MSEE from NJIT in 2004. He began his career at Westinghouse Corporation as an electrical field engineer on large integrated electrical systems. In 1997, he accepted a position with Lockheed Martin in Moorestown NJ and began a prolific career in RF/Microwave Receiver, Exciter, and Synthesizer designs. In addition to executing detail circuit designs, Mr. Delos has also led multi-disciplined design teams on highly integrated RF and mixed signal subsystem designs. His current interests are focused in RF and Analog designs with frequencies ranging from audio to microwave applications. The quest for high performance in reduced footprints led to detailed RFIC designs and in 2012 he was transferred to the Lockheed Martin RFIC Design Center.
References
[1] Gardner, “Phaselock Techniques”, 3rd Edition, Wiley, 2005
[2] Banerjee, “PLL Performance, Simulation, and Design”, 4th edition, 2006
[3] Wolaver, “Phase Locked Loop Circuit Design”, Prentice Hall, 1991
[4] Brillant, “Understanding Phase Locked DRO Design Aspects”, Microwave Journal, 1999
[5] Kalita, Bexboruah, “Modeling and behavioral simulation of noise transfer characteristics of a 2 GHz phased-locked loop for frequency synthesizer”, International Journal of Modern Engineering Research 2011
[6] ADS PLL Examples, “PLL Phase Noise”, Keysight Technologies
[7] “Phase Noise Characterization of Microwave Oscillators, Phase Detector Method”, Agilent Product Note 11729B-1.
[8] Rohde, “Microwave and Wireless Synthesizers, Theory and Design”, Wiley, 1995
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