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Eliminate High-Speed ADC Flicker Noise with Chopper Upgrade

Parent Category: 2015 HFE

By Tommy Neu

Modern high-speed analog-to-digital converters (ADCs) are primarily moving into more advanced CMOS process nodes to increase sampling rates and reduce power consumption as much as possible. However, this move away from traditional, bipolar transistor-based ADC designs comes with a big drawback. The low frequency 1/f noise or flicker noise of CMOS transistors is significantly worse compared to that of bipolar transistors.

The 1/f noise corner of bipolar transistors is around 100 kHz, while for CMOS transistors it ranges anywhere from ~10 MHz to ~1 GHz, depending on the process geometry. The cause of flicker noise is complex. A simplified model is based on the trap density in the oxide-silicon surface. Electrons get into the traps, but get released at a lower frequency. If the trap density is reduced for the same amount of carriers, flicker noise will be reduced as well, because the probability of carriers getting into the traps reduces. Therefore, the 1/f noise corner moves lower in frequency. The amount of carriers stays constant, if the width-to-length (W/L) ratio of the transistor stays constant. Alternatively, trap density is reduced by increasing the area. As such, a lower 1/f noise corner requires an area increase (larger transistor size) with the same W/L ratio.

Higher Noise Corner

Unfortunately, moving into smaller process geometries goes in the opposite direction, resulting in a higher 1/f noise corner. This severely impacts the performance of systems utilizing information contained in the area of close-in phase noise around DC. For example, motor controllers of high-power and precision motors use frequencies and its harmonics of only a few hundred kilohertz (kHz). Zero intermediate frequency (0IF) complex receivers may employ carriers with only tens of kHz offset. Thus, the 1/f noise performance of the high-speed ADC is crucial for these applications. As a result, modern high-speed CMOS ADCs, such as the 14-bit, 125-MSPS ADC3244, get outfitted with design enhancements like an internal analog chopper front-end, which combines the low-power CMOS ADC with very good 1/f noise performance.

Chopper Front-End Circuit Implementation

Chopper circuits have been used for more than 30 years. Nowadays a ‘chopper’ refers to many different switching circuits. Originally, the chopper was used to convert a fixed DC input to a variable DC output voltage. The idea of using a chopper circuit with CMOS ADCs is based on the same concept where the unwanted 1/f noise is transferred to a different frequency, as far away as possible from the wanted signal itself (typically to the Nyquist limit) (Figure 1). The ADC in our example uses an analog, passive mixer prior to the actual ADC-sampling network to accomplish this purpose. High-fidelity audio converters use the same concept, but employ a high-resolution (typically 24-bit) delta-sigma ADC, versus a pipeline ADC.

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Figure 1 • Wanted signal in the presence of 1/f noise.

The low-frequency input signal first gets shifted to Fs/2 using an on-chip passive mixer that operates at half the ADC clock frequency. Next the input signal gets sampled, as with any other data converter, except the low-frequency input signal now resides at Fs/2. In the sampling process, the unwanted 1/f noise of the ADC-sampling network gets added to the spectrum of the input signal. This operation is followed by a mixing block in the digital domain. The output spectrum is mixed once more with Fs/2, which now shifts the original wanted signal back near DC, and the 1/f noise near Fs/2. As a result of this exercise, the input signal is where it is expected and unaffected by the unwanted 1/f noise, which is placed on the opposite end of the Nyquist zone (Figure 2). At this stage, any 1/f noise contribution from the analog front-end signal chain is already combined with the wanted input signal and does not get shifted to Fs/2.

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Figure 2 • Chopper implementation in a high-speed data converter.

 

Measurement Comparison of Chopper Front-End

A comparison of the fast Fourier transform (FFT) output spectrum of the ADC in our example with the internal chopper enabled and disabled is illustrated in Figure 3. The low frequency 1/f noise is clearly visible when the chopper is disabled. Once the chopper is enabled, the flicker noise around DC is shifted to Fs/2, while the input signal remains untouched at 10 MHz. However, the FFT spectrum also reveals an additional byproduct of the chopper circuit. Besides shifting the input spectrum, the passive mixer generates a tone at Fs/2, also known as the local oscillator (LO) feedthrough, since the LO input is coupled into the output spectrum. However, when digital post-processing filters are implemented on the data, a likely scenario when analyzing DC and near-DC information, the transposed 1/f noise and LO feedthrough will be rejected.

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(a)

 

1505 HFE flicker fg04Figure 3 •

(b)

High-speed CMOS ADC compared with off (a)/on (b) chopper front-ends.

The low-frequency improvement from the chopper circuit becomes even more obvious when overlaying the two FFT plots directly on top of each other and changing frequency axis to a log scale (Figure 4). This reveals the ADC’s 1/f noise corner of about 10 MHz, and clearly shows the noise floor improvement between 3 kHz and 10 MHz.

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Figure 4. Low-frequency noise comparison between a chopper on and off.

Disadvantages of Employing a Chopper Front-End

The primary drawback for which a system engineer needs to be cognizant is the LO feedthrough when using a high-speed ADC with a chopper input. A large tone at Fs/2 can potentially limit an automatic gain control (AGC) loop when using a large amount of front-end gain for capturing a very small amplitude input signal. In that application, the LO feedthrough needs to be removed with a digital filter prior to the AGC function.

Since the mixer is passive, the additional power consumption from the chopper is very minimal and no additional signal-to-noise ratio (SNR) or spurious free dynamic range (SFDR) degradation should be expected.

Summary

As modern high-speed data converters are taking advantage of smaller process nodes for lower power consumption and faster clocking rates, ADC design engineers are implementing circuit enhancements to improve the few disadvantages associated with finer CMOS process geometries. A chopper front-end, as implemented in the ADC3244 for example, is a great way to drastically improve the unwanted flicker noise for applications where information of interest is in the very low frequency range.

References

1. Razavi, Behzad. Design of Analog CMOS Integrated Circuits, ISBN 0-07-238032-2, McGraw Hill

2. Download the ADC3244 datasheet

3. Here’s more information about TI’s high-speed data converters

4. TI E2E™ high-speed data converter forum

About the Author

Thomas Neu is a systems engineer for TI’s high-speed data converters group where he provides applications support. Thomas received his MSEE from Johns Hopkins University, Baltimore, Maryland. He can be reached at ti_thomasneu@list.ti.com.

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