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VSWR-Tolerant Push-Pull Class DEodd/CMCD RF PA

Parent Category: 2016 HFE

By David Pacholok, Paul Reich, and Jim Spangler

The push-pull Class DEodd (also called CMCD) PA has a rather long and interesting history, dating back to patent No. US2579374 issued to Donald V. Edwards (Figure 1)[1]. The year was 1947, the same year as the invention of the bipolar transistor. Edwards mainly intended his teachings to be used as a self oscillating high efficiency power converter, but described an amplifier version in his drawings.

Later, his basic circuit, using the rather slow Silicon bipolar parts of the day, saw widespread use in the early days of electronic fluorescent ballasts manufactured by Triad-Utrad/Magnetic (now Universal Lighting), Philips/Advance and others. Millions of these ballasts were produced roughly from 1977 through today configured as a power oscillator. As Vertical MOSFET technology improved, and dropped in price, the Edwards Converter slowly diminished its volume in the lighting market.

In 1975 Nathan Sokal invented the Class E Converter, and taught the world the concept of the 100% efficient RF power amplifier in a novel, elegant single ended form [2]. Since then many researchers have invented, or at least reinvented, many other classes and subclasses of high efficiency PAs. The search for even more such classes continues today, mainly driven by the continuously exploding wireless market in the GHz range.

Introduction

This article is directed to the other end of the RF spectrum, that being below 30 MHz. This encompasses the LF (Low Frequency), MF (Medium Frequency), and HF (High Frequency) ranges which contain many communications bands and several important ISM frequencies used for plasma processing, medical cautery, plastic sealing, wireless power transfer, resin curing and so forth. Such applications normally require output powers of several 10’s to many 1000’s of watts. The switching devices used most in such applications are either low-cost Switchmode Vertical MOSFETS, or very rugged, high dissipation RF-designed MOSFETS whose performance comes at a price. Both types of devices normally operate from 100 to 300 VDC to provide high load impedance and thus lower passive component losses.

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Figure 1 • Edwards Converter using vacuum tubes, copy of the front page of patent.

Despite the high potential efficiency, simplicity and inherent harmonic cancellation of the Current Mode Class D (CMCD or push-pull Class DEodd) PA, it has seen little use in the power and frequency ranges above. In our work with this amplifier class we have found that it is extremely intolerant of load Voltage Standing Wave Ratio (VSWR), more so than most RF Switching PA topologies. Even 1.5:1 VSWR upsets commutation and reduces efficiency significantly. Higher VSWRs such as 3:1 result in gross over dissipation of the switches, and failure of low-cost Switchmode parts. Let us examine the causes of this power and efficiency loss:

CMCD Loss Under Reactive VSWR, Capacitive Example

Fig. 2a shows the basic circuit of such a 100 Watt-class PA, at 1.356 MHz, Vcc=100V, QLOAD =7, wherein the output filter is a simple parallel-tuned circuit which provides the needed open at the fundamental frequency and near short at odd harmonics. Fig. 2b shows the simulated switch I and V waveforms with a perfectly matched load, Fig.2c shows switch I and V at a point on a 3:1 VSWR circle: 300-J400 ohms.  Perfectly matched, the circuit operates at high efficiency ZVS during turn-on and turn-off with square wave current. At the 3:1 point ZVS is totally lost and the current waveforms become a switch disaster waiting to happen!

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Figure 2a. • Basic Simulation Circuit without a matching transformer and without any diodes into 500 Ω. The VSWR is 1:1.

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Figure 2b • Simulation waveforms with Drain Voltage, Vt, in Black and Drain Current, Id,  in Blue for the ideal circuit with a VSWR 1:1 the load is 500 Ω. 

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Figure 2c. • This is a simulation of the basic circuit, shown in Figure 2, without any diodes, driving into a capacitive 3:1 load. The black trace is the Vt Tank Voltage and MOSFET Drain Voltage, the blue trace with spikes is the Id Drain Current, exceeding 45 Amps.


The commutation phase angle of the parallel tank has changed due to the detuning effect of the capacitive VSWR, causing mistiming of the switches driven at the fixed 1.356 MHz frequency. For the component values shown in Fig 2a, the tank circuit is detuned by the load’s equivalent parallel admittance:

Zload = 300-J400 Series: (Y = .0012 - B.0016 parallel equivalent) added tank reactance Xc is 1/0.0016= -J625.

Solving for parallel equivalent capacitance of the reactive term by

C=1/(2πXC)  (eqn. 1)

we find 188 pf has been added in parallel with the tank resulting in its resonant frequency dropping to 1.287 MHz, or a period of 777 nS (nanoseconds). The original period at 1.356 MHz was 737 nS. The difference is 39.5 nS meaning that the switchover from Q1 to Q2 conduction will be early by this amount, which is 19.3 degrees. The switchover occurs at 160.7˚ degrees not the desired 180˚.  

At this time the drain voltage is:

Vcc * π * Sin(160.7˚) = 103.6 volts (eqn. 2)

in our example circuit, the first energy loss is:

E = (½)*C * V2 = 9.26E-6 Joules     (eqn. 3)

where C is the 1725 pF tank capacitor. Multiplying by frequency to get Watts dissipation, we get 12.6 watts per switch or over 25 watts switch loss for both FETs combined. The simulation in Fig 2c shows a narrow current spike that goes off the screen. Using our simplified FET model with 1.5 Ohms Rds-on about 45 amps peak can be expected.

The 2nd loss mechanism is due to the FET switches conducting the tank current for the 19.3 degrees. The Off FET conducts via its Body diode, the On FET through its enhanced channel, with both in series.

The Z of our tank is:

Z = SQRT(L/C)   (eqn.4)

Substituting our values, SQRT(8uH/1.725nF) = 68 ohms.

Vpeak = π * Vcc   (eqn. 5)

At Vcc = 100V, tank peak voltage is π x Vcc = 314 volts, resulting in a peak current of 4.62 amps. At the 160.7 degree switch-over, tank current is

4.62 * Cos(160.7˚)  = 4.36 Amps  (eqn. 6)

This 4.36 Amps is added to the 1.0 amp 50% square wave that would normally flow through the FET at 1:1 VSWR causing extra dissipation. This dissipation by

P = I2R * duty cycle (eqn. 7)

is about (5.4^2 x 1.5 ohm) x 19.3degrees / 360degrees = 2.4 Watts per FET. This does not include the forward body diode drop of the opposite FET.

Taken together, the FETs see about 30 extra watts of dissipation. Similar commutation and loss issues occur at other load phase angles, such as when the Push-pull Class DEodd is exposed to an inductive VSWR.

A word of caution about the body diode of Vertical MOSFETS is in order here: This “diode” is really a parasitic NPN transistor with its B-E junction more or less shorted by the manufacturing process.  If current is sent through this or any PN junction “diode” it accumulates minority carriers which persist until natural recombination takes place.  This takes typically between several hundreds of  nSec and several uSec. If the FET is turned off into high dV/dT before recovery is complete, the body diode is subject to forced recovery, current crowding, high dissipation and possible failure.  

In the late 1990s Server power supplies began dying mysteriously under low load in the middle of the night in a circuit known as the phase-shifted ZVS converter due to this cause. The semiconductor manufacturers responded with FETs having Body Diode Trr (Reverse Recovery Time) times reduced by a factor of 5 or more compared to standard devices.(ref 3). While these “designer FETS” solved the Server problem at 250KHz, allowing body diode conduction in the MHz region remains a potential FET killer.

Solutions Explored

Our first attempt was to take a lesson from D.V. Edwards and realize that tubes do not have a body diode or anti-parallel diode of any sort. A Cree “Zero Recovery” 1.7 A 600 V SiC Schottky diode was connected in series with each drain to prevent reverse current flow. This improved the drain current waveforms under capacitive and inductive VSWRs, but efficiency dropped from to 91% to 82% at 1:1 VSWR. Given the 1.7 volt drop of the SiC diode, an efficiency drop under 2% was expected.

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Figure 3 • Functional new circuit with test points added, Clamp Diodes, and Drain Diodes, and the 50 Ω impedance matching transformer for measurements. (VT =Tank Circuit Voltage, VD = MOSFET Drain Voltage. And ID = Drain Current.)

Waveform investigation of the drain terminals showed the cause: the diode caused the CDS of the FETs to peak charge to nearly the Pi x Vcc = 314 V peak, and the energy thus stored was dissipated at FET turn-on:

Dissipation is:

Pwatts = ½*Cds(Vds2) * Frequency  (eqn. 8)

= 0.5 x 60pF x 314^2 x 1.356E6 =  4.02 Watts/ FET, OR ~8 Watts for the converter.

We reasoned that connecting an inductance between the drain terminals to resonate out ONLY the Cds might be a solution, the main tank being diode isolated from the FET drain from 90 to 180 degrees of the off-time. The inductance was calculated from the equation:

L=1/(4π 2F 2CDS)= 138uH    (eqn. 9)

This was tested in simulation and on the bench. The simulation showed very near ZVS at 1:1 VSWR with our simplified FET model. At Vcc=25V, commutation as tested was ZVS but higher voltages drove the varactor-like Cds down, and we settled on 200 uH being a good empirical choice. The 1:1 VSWR efficiency increased to 89%, near that expected. Capacitive and Inductive VSWRs at 3:1 provided low stress current waveforms, as did purely resistive VSWR.  

Then a major issue with reactive VSWR was then found: The drain voltage waveforms no longer obeyed the Vpeak = π x Vcc equation. (eqn. 5)  Peak voltages in excess of  5 x Vcc were observed. The reason for this is that the Classic (No series Diodes) push-pull CMCD is a bidirectional converter wherein the body-source diodes recycle excess tank circuit energy resulting from the reactive portion of the load. [4]

Final Circuit

Our final solution is a bit “brute force” as shown in Fig 3. A secondary winding was added to the 200 uH commutating tank inductor that formed a 3:1 step-down transformer. By rectifying this and feeding the DC back to Vcc, a 3:1 energy recycling drain voltage clamp was formed. The 200uH commutating tank inductor consisted of 90 turns # 30 AWG on a Ferroxcube 4F1 I-core solenoid, 30 turns of #21 were overwrapped with a layer of Teflon tape as insulation.

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Figure 4 • Classic CMCD circuit without any in series switch diodes, voltage clamp diodes, but with an impedance matching transformer for 50 Ω. (VT =Tank Circuit Voltage, ID = Drain Current.)

This secondary was connected to a diode full bridge consisting of 1.7 amp 600 V SiC diodes. This held the drain voltage below 350 Vpeak for any point on the 3:1 VSWR circle. Due to the 7.1 uH leakage inductance between primary and secondary, the clamping action is soft. Higher reactive VSWRs create higher drain voltages and more current through the clamp winding.  

Comparison of Results with Classic CMCD

The drain current and voltage waveforms for 2 reactive points on the 3:1 VSWR circle are shown. In Figs 3a,b and Figs 4a,b we compare waveforms from our circuit in “a” figures, with Classic CMCD waveforms in “b” figures. In the caption below each waveform figure we provide measured efficiencies. In this final version we are satisfied with the clean current waveforms, and the efficiency improvements achieved.

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Figure 3a. Voltage and Current Waveforms for the circuit shown in Figure 3. The load is capacitive with a VSWR 3:1.

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Figure 3B. Voltage and current waveforms taken with a capacitive VSWR of 3:1 as shown in circuit of Figure 4.

High VSWR Results

The final circuit was tested at 6:1 VSWR. Losses (as CDS energy) were greater due to FET switching occurring at higher voltage. The peak drain voltages also increased to roughly 420 V peak. This voltage increase must be considered when choosing switches using this circuit. Compared to the classic CMCD topology the low stress drain current waveforms are maintained, as shown in Figs 5a,b and Figs 6a,b.

As purely resistive VSWR does not cause tank detuning and commutation mistiming, these waveforms are not presented. Practical implementations of the CMCD often include an inductor in series with the load to limit power with low load resistances or shorts. In such cases purely resistive VSWR will cause mistuning and commutation issues as presented above.

Efficiency

The efficiency was measured for each of the four non-resistive loadings. The Efficiency Table is a summary of the results.   

Efficiency Table

Circuit LoadingNew circuit with diodes(Fig. 3)Old circuit without diodes (Fig. 4)

Capacitive VSWR 3:182 %50 %

Inductive VSWR 3:175 %71 %

Capacitive VSWR 6:171 %42 %

Inductive VSWR 6:162 %51%

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Figure 4a • New circuit shown in Figure 3, with an inductive load and a VSWR 3:1.

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Figure 4b • Inductive Load with a VSWR 3:1 using the circuit shown in Figure 4.  Please note the ringing since there are no drain diodes.

Gate Drive Timing Tolerance

As an unexpected benefit, the final VSWR-tolerant CMCD converter can be driven with gate duty cycle in excess of 50%, or with large timing skew between FETs 1 and 2 gate drive. While the Classic CMCD Converter shorts out the Main Tank under these conditions, causing the two types of power/efficiency losses detailed above, the SiC diodes prevent this much like the TUBES in the Edwards Converter.

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Figure 5b. Capacitive VSWR 6:1 using Figure 4, classic CMCD:  note the ringing.

Diode Notes

This diode isolation is only as good as the diode’s capacitance under reverse voltage; in the case of the CMCD1.760 SiC diodes this is about 10 pF at Vr = 100V. These diodes are true Shottky diodes, their reverse current is due only to charging the non-linear junction C under reverse bias, they have no Ta where a diode is essentially ON in reverse, and no Tb wherein energy is lost by the diode going through a dissipative forced recovery period as happens with PN junction devices. Panasonic and Transphorm both announced ultra-low capacitance 600V GaN diodes having only 0.8 V forward drop in the 2012-2013 time frame, but these devices seem to not be commercially available. [5, 6]

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Figure 6a. This shows the voltage and current waveforms for an inductive load with a  VSRW 6:1 using new circuit shown in Figure 3.

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Figure 6b. Inductive load with a VSWR 6:1 using the Classic CMCD shown in Figure 4. Please note the ringing since there are no steering or clamping diodes.

Circuit Limitations

It should be understood that at inductive and capacitive VSWR the final circuit does not achieve true ZVS at both turn-on and turn-off as it does with a non-reactive load. In the capacitive 3:1 VSWR example, the Cds remains charged to about 100 volts, and this energy is dissipated as heat. In the example circuit the power dissipation due to Cds (about 60 pF) was 0.432 Watts/FET. In contrast, the Classic CMCD swallows the ENTIRE stored tank energy in the 1725 pF tank capacitor for a loss of 12.4 W per FET.  

The implication of this is that this new circuit provides real benefits in a non-Cds-limited situation. Cds limitation occurs when most or all of the tank capacitance is the switch Cds, not in an external tank capacitor. This limits its use to below 30 MHz with current semiconductor technology. A more obvious limitation is supply voltage.  At Vcc= 300V, the efficiency losses in the diode drops, Vf, are about 0.6%, rising to about 2% in our Vcc=100V example.  Using this circuit at progressively lower Vcc levels incurs progressively higher losses.

Max Eff = (Vcc-Vf) x 100%     (eqn. 10)

Another limitation is circuit complexity; we had hoped for a simpler solution. 6 SiC diodes are needed as well as a commutating inductor/transformer with tightly coupled windings. The distributed capacitance and leakage inductance limit maximum frequency. As to cost, it should be pointed out that the SiC diodes used in this circuit are usable with a Vcc up to 300V at 2 amps drain current, i.e. a 600 watt RF power supply. These diodes are $0.50 each in 5000 quantity, so we feel our goal of low BOM cost is met. In comparison, automatic load matching systems normally required are EXPENSIVE. In some applications we hope that our work may eliminate them entirely, or at least reduce their requirements and cost.

Conclusion

We designed, analyzed, and tested a CMCD RF amplifier, using diode networks and an added commutating tank circuit to increase transistor tolerance to load mismatch. We noted that peak current and dissipation due to impedance mismatches were reduced with this configuration. We hope that our work will inspire others to investigate this topology as an inexpensive means to achieve greater VSWR tolerance with low cost semiconductors.  

References

1.Edwards, US Patent no. 2579374

2. Andrei Grebenennikov and Nathan O. Sokal. “Switchmde RF Power Amplifier”; ISBN: 978-0-7506-7962-6, Oct. 2007

3. Fairchild Application Note, AN-7536, Nov. 23, 2005 

4. Abbasian, Sadegh, “Radio Frequency Switch-Mode Power Amplifiers and Synchronous Rectifiers”, University of British Columbia, Oct 2015.

5. Panasonic Headquarters News Press Release, Sept 30, 2015.

6. Transform TPS30xxPK series GaN diodes datasheet.

About the Authors

David Pacholok has operated Creative Electronic Consultants LLC since 1981. He has been involved in Switchmode Power Conversion, Electronic Lighting Ballasts, RF power, Pulse Power, and Induction heating.  He can be reached @ 847-809-2786 (cell), 847-428-5676 (office), and at cecinduction@gmail.com.

Paul Reich is a freelance consultant and ham radio operator living in the Chicago area. His specialties are radio frequency design and simulation. In a previous life, he held various positions at Motorola, Inc. and the Chamberlain Group. Paul earned his BSEE in 1976, from MSU, Bozeman, MT.

Jim Spangler is President of Spangler Prototype Inc., an engineering consultation firm since 2009. Jim has been a Field Applications Engineer for nearly 30 years for Motorola Semiconductor, On Semiconductor, Cirrus Logic, and Active Semiconductor specializing in power electronics applications. Jim is involved with the several IEEE societies and PSMA planning the Applied Power Electronics Conference (APEC) for over 10 years. Jim has published many articles and conference papers for power electronics applications including Lighting Applications. Jim taught “Survey of Power Electronics” at Illinois Institute of Technology while in pursuit of his PhD. Jim can be reached at 847-961-8588 (cell) or jim.spangler@ieee.org and jim.spangler@spanglerprototype.com.

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