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Advantages of Platinum as a “Barrier” Metal on Thin Film Hybrid Microelectronics Substrates

Parent Category: 2016 HFE

By Joe Krasucki

Thin film coated substrates have been used for many years to fabricate hybrid microcircuits for DC to millimeter frequency applications. These generally passive microcircuit substrates are used for interconnecting various chip components to make a complete electronic circuit in a small and reliable package similar to printed wiring boards, but smaller. 

Thin film metallization systems or “stackups” used generally consists of gold/“barrier” layer/“gluon” layers on a hybrid substrate. The chosen metal “stackup” must meet several criteria:   

A. Conduct DC to Millimeter frequencies with little or no loss

B. Be compatible to normally assembly methods (wire bond, solder etc.)

C. Be metallurgically & chemically stable with long term reliability

D. No deleterious migration of metal up/down through the metal system.

Gold is the conductor of choice followed by a “barrier” metal between the gold and underlying “gluon” metal which attaches the whole system to the substrate.  The two main functions of the “barrier” layer material are: 

A. Prevent inter-diffusion of metals up or down through the metal system and the underlying substrate.

B. Prevent solder leaching of a eutectic or soldered component from the substrate.

C. To prevent wire bond problems and promote long term circuit reliability. 

Choosing a Barrier

The choice of a suitable “barrier” material is necessary. Fortunately there are two reliable barrier materials available: palladium and platinum. Both prevent metal diffusion or migration of between metal layers and underlying substrates. Also both are solderable and compatible with almost all currently available solders. Neither palladium nor platinum form oxides or migrate easily. Though extreme, palladium may, under long term high temperature exposure alloy with the top gold conductor metal. This is rarely encountered but can happen. 

Platinum, however, is a well-known “barrier” to metal migration and is eminently solderable with all normal solders encountered in the microelectronics technology industry. Significantly, it only alloys with gold at extreme temperatures not found in hybrid and passive component fabrication technology. The thickness of platinum normally used as a “barrier” layer is very robust 1250 – 2000 Angstroms (5-8 microinches). Platinum may be described euphemistically as the “Platinum Standard” of barrier materials. Platinum layers of 1250 – 2000 Angstroms thickness are generally used. It is easily vacuum sputter coated onto substrates and due to the “thin-ness.” Platinum is economical, at only ~$0.04 per 2” x 2” substrate. (Based on $1250 per Tr. Oz. fab cost.) 

Fab/Assembly

A brief description of the fabrication/assembly process and materials for microcircuits is as follows: Chip mount: solder (surface mount assembly), eutectic (Au/Sn) or conductive epoxy attaches components such as IC’s, MIMICS, transistors, diodes etc. or passive components such as capacitors, resistors/networks or inductors to the interconnect substrate. When chips are solder-mounted on the substrate using various solders or gold tin eutectic bonding is used, the circuits are subjected to high temperatures. Gold generally dissolves in the solder or gold tin eutectic mixture. This is where a good “barrier” material is crucial in order to prevent leaching of the solder and conductor films from the substrate. This is where a platinum “barrier” serves as the best choice. 

Substrate dielectric materials most commonly are aluminum oxide (alumina), quartz, glass and beryllia or aluminum nitride for higher power usage due to their higher thermal conductivity vs alumina et al. Substrate material thickness varies depending on assembly handling needs, material dielectric constant, RF frequency and other factors. Standard thicknesses often used are 0.005”, 0.010”, 0.015” and 0.025”. Other thicknesses are available as custom. 

Surface finish of the substrate is dictated by the circuit frequency and interconnect line width/spaces tolerances required. High frequency circuits of >5Ghz require a 1 micro inch surface finish average (SFA) for low loss and optimum performance whereas DC to low frequency circuits operate satisfactorily with less costly “as fired” alumina having an ~4 micro inch SFA. For fine line definition of conductor patterns such as those present on Lange couplers, filters, etc. Polished substrates of <1 micro inch SFA are required. Otherwise, tolerances and performance will NOT be met. The cost difference between polished and “as-fired” alumina is approx. 4 to one.  

Solder/Wire

Connecting the mounted components to the interconnect metallization uses solder, and/or wire bonding. Wire bonding is usually performed using gold or aluminum wire of 0.0005” to 0.005” diameter with 0.001” gold wire being the dominant bond wire used. In some cases “ribbon” bonding using 0.001” thick x up to 0.005” wide gold ribbon is used, particularly on RF or power circuits.

Where wire bonding or soldering is used, the metal system “stackup” on the substrate is very important. Thin film gold, the dominant substrate interconnect metal used, may be spec’d from a  thickness of 1 – 5 microns depending on power requirements or RF “skin depths” needed for high frequency applications. Thicknesses of 2.5 to 5.0 microns gold are most commonly chosen by the circuit designer.

Gold does not adhere to alumina, quartz, glass, beryllia or aluminum nitride substrates and thus a “gluon” adhesive layer compatible with both barrier material and the underlying substrate material. Adhesion gluon layers commonly used are chrome, nichrome, tantalum nitride, titanium or titanium/tungsten with the thickness used commonly between 200 – 800 Angstroms. Tantalum nitride or nichrome will often serve as both an adhesion layer and resistor layer especially on resistor networks such as attenuators, ladder networks etc.

Unfortunately, nichrome or chrome, under thermal processing experienced during resistor heat treatment/stabilization & chip mounting, causes nickel or chrome to migrate up through the overlying gold conductor layer to some extent. This occurs interstitially along the gold grain boundaries. Care must be taken with heating/baking on a substrate containing chrome or nickel from underlying chrome or nichrome to reach the top surface where they will oxidize to nickel and chrome oxide. This is especially true if nickel is used as the barrier metal. 

Thin, Transparent

These nickel and/or chrome oxides are generally thin, transparent and invisible even under high magnification. These surface oxides may vary in thicknesses from 20 Angstroms up to 200 Angstroms or more. Their presence and thicknesses have been verified during assembly difficulties and failure analysis many times by the author using Auger Spectroscopy. Oxides of > 30 Angstroms have been found to cause a progressive inability to wire to the gold conductor. Even if bonding is possible, the bond pull strength degrades often below the MIL Spec Std. of >4 grams. Long term reliability of the entire circuit is thus compromised.  

Barrier Materials

Solder barrier materials available are nickel, nickel/vanadium, palladium or platinum. (Note: thin films of tantalum nitride, nichrome, chrome, titanium or titanium/tungsten are NOT solderable.) Typically, barrier layers may be from 800 to 2000 Angstroms thick (3-8 microinches).

Nickel or nickel/vanadium are the common solder barrier materials used in the industry. However, if the time/temperatures exposure during thermal heat treatment and assembly is lengthy or “excessive,” some nickel and/or chrome WILL migrate upward through the gold conductor layer. Depending on the gold thickness, nickel and/or chrome can reach the top surface of the gold where it will oxidize. This upward diffusion or migration to the surface is a function of the time/temperature exposure and gold thickness. Chrome and/or nickel oxides on the surface will compromise or prevent wire bonding to the gold conductor interconnect. Inability to bond is a readily apparent defect, but initially successful wire bonds may not pass MIL STD 883 bond pull testing (>4 grams) while those that do pass may fail after burn in or high temp storage. This is a reliability issue for military or hi-reliability circuits over the long term. This is where choice of platinum as a barrier metal comes in.

Platinum, while clearly being the superior barrier film for microelectronics, is not used by many passive component or substrate manufacturers due to the incorrect impression of higher cost, but mostly due to platinum’s difficulty in etching.  It is difficult to wet etch. Only “Aqua Regia” (conc. nitric acid/hydrochloric acid) is available as etchant. But Aqua Regia destroys photoresist making it incompatible with normal thin film pattern etching.  However, there are two means to pattern etch Platinum: 

1. Ion Beam Milling

2. RF Plasma Reactive Gas Ion Etching (RIE)

Ion beam milling is the method of choice between the two because it does “straight wall” etching and does not use or produce environmentally sensitive chemicals. Reactive ion etching uses exacting conditions requiring elaborate safety measures, exhaust emissions scrubbers, noxious chemicals etc. and entails significant capital investments. For these reasons RIE is mostly used in the semiconductor Industry where its costs and controls are justifiable. 

Ion milling on the other hand does not utilize hazardous chemicals nor involve environmentally sensitive chemicals and byproducts. Ion beam milling utilizes inert argon, a normal constituent of air which is present all around us. There are no hazardous materials involved or created. Fortunately, a service oriented vendor with rapid turnaround of ion beam substrate processing and patterning capabilities is available. Ion Beam Milling, Inc., of Manchester, NH was established 35 years ago to meet this and other ion milling needs. As one of their standard metal systems, Ion Beam Milling regularly processes substrates with platinum barrier layers.

Conclusion

In conclusion, the solderability of chips/components having a platinum barrier layer allows for numerous rework cycles per MIL STD 883 M2003, without the fear of leaching. It also enhances wire bondability during the wire bond process. An added plus is that there is NO long term bond degradation or weakening due to metal migration. This definitely enhances long term circuit reliability.   

Clearly, whenever possible, passive components and substrates having a platinum barrier layer should be chosen for your particular microelectronic circuit needs.

About the Author

Joe Krasucki is an Engineer/Manager retired from BAE Systems, Inc., with 46 years’ experience in design, fab and applications of Semiconductor, Hybrid and Modular DC to Microwave circuitry.  He has worked at Texas Instruments, United Aircraft, Mini-Systems, Piconics, and BAE Systems Inc. Much of his work has been on Military Electronics from DC to Millimeter Wave systems for aircraft, satellite and weapons systems. Some of the programs are: F-22, F-35, F-18, MX, Trident, Longbow, THAAD, and numerous classified programs. Joe’s specialty has been Thin Film Technology and High Frequency circuit fab. He holds a BS and MS in Chemistry and Chem E as well as an MA in Psychology. Joe resides in New Hampshire, where he continues to do consulting work and teaching.

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