Sunday, April 21, 2019
Login

Articles

A Simulation-Based Design Flow for Broadband GaN Power Amplifier Design

Parent Category: 2016 HFE

By Ivan Boshnakov, Malcolm Edwards, Larry Dunleavy, Isabella Delgado

The purpose of this note is to demonstrate a simulation-based methodology for broadband power amplifier design using load-line, load-pull, and real-frequency synthesis techniques. The design shown in this application note is a Class F amplifier and was created using the Qorvo 30W GaN HEMT T2G6003028-FL transistor. Goals for this design were: a minimum output power of 25W, bandwidth of 1.8 - 2.2GHz, and maximum power added efficiency (PAE). The design procedure was performed using the Modelithics GaN HEMT non-linear model for the Qorvo transistor mentioned above; Modelithics Microwave Global Models for the passive components in the matching network design; and the Amplifier Design Wizard (ADW) from AMPSA (all tools available within suitably configured NI AWR’s Microwave Office).

Design Overview

For this design methodology it is crucial to have access to the intrinsic device channel voltage and current. Such capabilities are available in the advanced non-linear Modelithics GaN models. The design begins with measurements of the voltage and current at the drain-source intrinsic current generator within Microwave Office. The near optimum load-line, impedances of the fundamental frequency, and harmonic impedances for a single frequency are located for the required mode of operation. The impedance regions are then extracted using load-pull simulations. Using ADW, the “real-frequency” synthesis of the matching networks can be quickly realized simultaneously for the fundamental and harmonic impedances across a wide bandwidth. These fully laid-out matching networks can then be exported to MWO for the remainder of the design optimization, non-linear analysis, and electromagnetic (EM) simulation.

Design Process

To begin the design process, a schematic to bias and stabilize the transistor must first be drawn. Once the conditions required for stability and biasing are established, the initial load-line analysis and harmonic impedance tuning can be performed (Figure 1).

1603 HFE powerAmp image1a

1603 HFE powerAmp image1b

Figure 1 • Top – Schematic to bias and stabilize transistor. Bottom – IV curve simulation schematic.

 

Initial Load-Line and Harmonic Impedance Tuning

First, a line is drawn on top of the IV curves to approximate the near optimum load-line for the fundamental frequency (the maximum swing of the RF voltage and current before hard clipping occurs). Then the dynamic load-line, defined using meters located within the model to monitor the intrinsic drain voltage and current and superimposed on the IV curves by the IVDLL measurement, is tuned to be a straight line and parallel to the drawn line. The tuning at a chosen frequency is performed by tuning the magnitude and phase of the output tuner impedances. At this stage, the harmonic balance simulation is limited to just a single harmonic—the fundamental frequency. Additionally, the harmonic impedances of the output tuner and all the impedances of the input tuner are set to 50Ω. The final results of the tuning can be seen in Figure 2.

1603 HFE powerAmp image2

 Figure 2 • IV curves with dynamic load-line superimposed.

 

Once the impedance of the fundamental frequency is known, the second and the third harmonic impedances presented to the intrinsic drain can be tuned according to the desired mode of operation. In the case of this application note, Class-F operation is desired, meaning that the second harmonic impedance is tuned to a short circuit and the third harmonic impedance is tuned to an open circuit (Figure 3).

1603 HFE powerAmp image3

Figure 3 • Smith chart view of the fundamental and harmonic impedances of the output tuner.

The fundamental impedance of the input tuner is then made to be a conjugate match to the S11 of the transistor and stability / bias network. This will provide the best match and therefore, maximum gain. The harmonic impedances of the input tuner are set to 50Ω.

Now that all of the impedances have been tuned, a final harmonic balance simulation (using three harmonics) is performed to confirm the design is in the desired mode of operation. Figure 4 and Figure 5 show the classic shapes of a Class-F mode design.

1603 HFE powerAmp image4

Figure 4 • Final dynamic load-line after harmonic impedance tuning.

 

1603 HFE powerAmp image5

Figure 5 • Intrinsic voltage and current waveforms after harmonic impedance tuning.

Load-Pull Impedance Extraction

With the previously defined input and output impedances, load-pull simulations are performed to produce contours first for maximum power (Pmax) and then for maximum drain efficiency (DCRF). The same schematic is used for the load-pull simulations as for the initial tuning except for the addition of an XDB control element (Figure 6). This provides contours which are not only at a constant power, efficiency, etc., but also at a constant gain compression.

1603 HFE powerAmp image6

Figure 6. Load-pull simulation schematic. Notice that the schematic is identical to that of Figure 1, however the input and output impedances have been updated and the XDB component has been added.

In Figure 7, the contours at the fundamental frequency for both maximum power and efficiency have been superimposed in order to define a region of compromise for mutually acceptable power and efficiency. In this case, an output power 1dB below the maximum and an efficiency 5% below the maximum has been chosen. In the plot shown, a circle defining this region is placed by using an equation to define the acceptable area of the fundamental frequency impedance for the synthesis of the relatively broadband output network.

1603 HFE powerAmp image7

Figure 7 • The load-pull contours of the fundamental frequency for maximum power (blue) and drain efficiency (magenta) have been plotted in the same Smith chart. The green circle defines the region of mutually acceptable power and efficiency.

Next, load-pull simulations for second and third harmonic frequencies are performed at the two impedances that provided the maximum power and maximum efficiency in the load-pull simulation of the fundamental frequency. The results for both load-pull simulations at the second and third harmonic can be seen in Figure 8. For the simulation at the second harmonic frequency, the optimum maximum efficiency in both cases is the same and the contours are essentially the same. A line is drawn to bound the area with acceptable performance. In this case, the acceptable region is below the line. For the simulation at the third harmonic frequency, the optimum maximum efficiency is again the same in both cases. However, the contours differ somewhat. Fortunately, the effect of varying the third harmonic impedance is small and an acceptable region is easily defined above the drawn line.

1603 HFE powerAmp image8a

1603 HFE powerAmp image8b

Figure 8 • Top – Plot of load-pull contours for the second harmonic frequency at the fundamental impedances for maximum power and drain efficiency. The acceptable region is below the drawn line. Bottom – Plot of load-pull contours for the third harmonic frequency at the fundamental impedances for maximum power and drain efficiency. The acceptable region is above the drawn line.

 

The described impedance extraction process is performed for a few frequencies across the desired bandwidth. In the case of this application note, simulations for 1.8GHz, 2GHz, and 2.2GHz were sufficient. It is important to note that this is a streamlined method of extracting the fundamental and harmonic impedances relies on access to the voltage and current across the intrinsic generator. Access to the intrinsic device nodes allows for a near optimum tuning of the fundamental load-line (impedance) and fixing the harmonics impedances for a particular mode of operation at the outset of the design flow. If the transistor model was a black box or the intrinsic access was not used, the load-pull impedance extractions would need to be performed for far more iterations. First, load-pull for the fundamental frequency has to be done with the harmonics set to 50Ω. Then, the load-pull has to be performed for harmonic loads and then with the newly found harmonic impedances. For the highest performance, load-pull for the fundamental is again repeated. More iteration is needed for the harmonics, and at that point one might want to stop the iterations. The issue with this approach, other than the number of iterations required, is the uncertainty that optimum loads were actually defined, and nothing will be known of mode of operation.

Matching Network Synthesis

Once all impedances have been determined, ADW will be used to synthesize the broadband matching networks. The required fundamental and harmonics impedance areas across the desired bandwidth are defined in the corresponding facilities of ADW are shown in Figure 9. The fundamental impedance areas for each frequency are circles on the Smith chart. The harmonic impedance areas are sections of the Smith chart.

1603 HFE powerAmp image9a

 

1603 HFE powerAmp image9b

1603 HFE powerAmp image9c

 

Figure 9 • Top - Examples of the termination definition facilities in ADW. Bottom – Smith chart view of desired termination impedances (red, grey, pink, and blue) versus achieved impedances (green).

 

Based on the impedances input into ADW, an initial hybrid microstrip/lumped component output matching network was synthesized (left image in Figure 10). The initial design is then exported into ADW’s analysis facility for the addition of all decoupling components, optimization and layout manipulation. The final output matching network design can be seen on the right in Figure 10. The same process is performed for the input matching network and both designs are exported to MWO to finalize the design.

1603 HFE powerAmp image10a

1603 HFE powerAmp image10b

Figure 10 • Top– Initial hybrid microstrip / lumped element output matching network created in ADW. Bottom– Final output matching network after decoupling elements, optimization and layout manipulation is complete.

Finalizing the Design

Once the matching networks are in MWO, Modelithics models are substituted for the surface mount lumped element models used in ADW. Final linear, harmonic balance, EM, and DC simulations are then performed to fine-tune the design. The described design process typically eliminates the need for optimization. The final layout and design performance can be seen in Figure 11 and Figure 12, respectively. Figure 13 shows the simulated intrinsic device channel voltage and current waveforms at 1.8GHz, 2GHz and 2.2GHz. It can be seen that the mode of operation of the final design is very close to Class-F across the required bandwidth. It could be claimed that the described method of design achieves an extended continuous Class-F mode of operation [1].

1603 HFE powerAmp image11

Figure 11 • Final layout for the Class-F amplifier design.

1603 HFE powerAmp image12

Figure 12 • Final simulated performance for the Class-F amplifier design.

 

1603 HFE powerAmp image13a

 

1603 HFE powerAmp image13b

1603 HFE powerAmp image13c

Figure 13 • Simulated intrinsic device channel voltage and current wave forms at 1.8GHz (top ), 2GHz (middle), and 2.2GHz (bottom).

 

Measurement Results

The Class-F power amplifier design presented in the design flow above was built and tested. An image of the assembled amplifier can be seen in Figure 14. The measured results presented in Figure 15 - Figure 18 are presented without any tuning. As evidenced by the following figures, excellent measurement to simulation agreement was achieved without any on-the-bench tuning.

1603 HFE powerAmp image14

Figure 14 • Assembled Class-F amplifier design.

1603 HFE powerAmp image15

Figure 15 • Simulated versus measured output power (red), PAE (blue), and S21 (green). Lines show simulated performance, symbols show measured data.

1603 HFE powerAmp image16

Figure 16 • Simulated versus measured small signal S-Parameters.

1603 HFE powerAmp image17

Figure 17. Simulated versus measured output power (left) and PAE (right).

1603 HFE powerAmp image18

Figure 18. Results of a preliminary yield analysis showing the effect of part value tolerances on PAE. Performed with 5% tolerance on all capacitors in the output matching network.

Although there is a small difference in simulated versus measured output power, this is to be expected as in reality there would be slightly more losses in each element, the transistor would heat up, and the models of the transistor and any other component could not be perfect. However, the difference in PAE is somewhat more substantial. In an attempt to resolve this discrepancy, a preliminary yield analysis was performed on capacitor part values in the output matching network (Figure 18). All capacitors were assigned a 5% tolerance. It is perceived from the yield analysis that some initial tuning could reduce, if not eliminate the discrepancy in PAE.

Conclusions

A streamlined practical design method for a broadband high-efficiency RF power amplifier was presented. Using Modelithics transistor models with access to the reference planes at the intrinsic generator allows for a new approach and shortened process of extracting the fundamental and harmonic impedances to obtain the desired performance. The new approach is to pre-tune the fundamental and harmonics impedances presented to the intrinsic current generator before performing load-pull simulations.

The efficiency and creativity of the design process is also substantially improved by using the Amplifier Design Wizard which is the only commercially available “real-frequency” and “real-world” matching network synthesis tool. It also provides many levels of automation to drastically reduce the amount of time required to create and manipulate the schematics and layouts.

References

[1]Vincenzo Carrubba, Alan. L. Clarke, Muhammad Akmal, Jonathan Lees, Johannes Benedikt, Paul J. Tasker and Steve C. Cripps, “On the Extension of the Continuous Class-F Mode Power Amplifier”, IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1294-1303, May 2011.

About the Authors

Ivan Boshnakov is with ETL Systems Ltd. Malcolm Edwards works at NI AWR. Larry Dunleavy and Isabella Delgado are with Modelithics Inc. Thanks to Adam Furman and Scott Skidmore of Modelithics for assistance with assembly and testing of the power amplifier example used in this note.

Contact Information

For information on accessing the Modelithics-Qorvo GaN Model Library or the Modelithics COMPLETE Library please contact Modelithics at sales@modelithics.com or via the web at modelithics.com.

March 2019

1903 HFE cover

The March 2019 Online Edition is now available for viewing and download!

Download March HFE PDF

Search

Web Exclusives

AWR

AWR logo

Live Class:  New NI AWR Software Training Course

NI AWR software will be featured in an equations and scripting training course this spring. The two-day class is offered in Santa Clara, CA, March 20-21 and in El Segundo, CA, April 16-17. To learn more and register, visit

awrcorp.com/news/trainings

System Simulation Primer for RF Link Budget Analysis

This white paper examines how a more rigorous link budget analysis of an entire system can be determined through simulation using Visual System Simulator™ (VSS) software and how performing link budget analysis enables designers to address losses, gains, and power levels to meet the operational requirements of radio communications systems. 

https://awrcorp.com/register/custom.aspx?crg=_whitepapersystem


Contact Us

Scott Spencer
Publisher
603-759-1840

Tim Burkhard
Associate Publisher
707-544-9977
Fax: 707-544-9375

Gary Rhodes
VP Sales
631-274-9530
Fax: 631-667-2871

Jeff Victor
Advertising Sales - Western U.S. - New Accounts
224-436-8044
Fax: 509-472-1888

Keith Neighbour
Advertising Sales - Central US
773-275-4020
Fax: 773-275- 3438

Sam Baird
Advertising Sales - UK and Europe
+44 1883 715 697
Fax: +44 1883 715 697

Zena Coupé
Advertising Sales - UK and Europe
+44 1923 852 537
Fax: +44 1923 852 261

Joanne Frangides
Advertising Sales - New Accounts & Product Showcase
201-666-6698
Fax: 201-666-6698

Insulated Wire Inc.

Insulated Wire Inc. is pleased to announce that following the retirement of a French delegate, IW Microwave Products Division President, John Morelli, has been appointed as the Secretary for IEC/SC46F, a subcommittee of IEC/TC46. IEC/SC46F is responsible for RF and Microwave Connectors and Components International Standardization.

Mr. Morelli, who is sponsored by Insulated Wire, brings significant RF/Microwave connector and component experience to the position, and we congratulate him on his new appointment. Mr. Morelli had been serving as the chief Technical Advisor for the US National Committee’s Technical Advisory Group to IEC/SC46F.

The US National Committee of the IEC is a fully integrated entity of the American National Standards Institute (ANSI).